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PL611-30XXXSI-R Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PL611-30XXXSI-R Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 7 page Preliminary PL611-30 Programmable Quick Turn ClockTM 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1 FEATURES • Advanced programmable PLL design • Very low Jitter and Phase Noise (< 40ps Pk-Pk typical) • Output frequency up to 375MHz CMOS. • Supports differential CMOS output to produce PECL, LVDS inputs. • Crystal inputs: o Fundamental crystal: 10MHz-30MHz o 3RD overtone crystal: Up to 75MHz o Reference input: Up to 200MHz • Accepts <1.0V reference signal input voltage • One programmable I/O pin can be configured as Output Enable (OE), or Frequency Selection input (FSEL), or Reference clock. • Single 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C • Available in 8-pin MSOP/SOIC, 6-pin SOT Green/ RoHS compliant packages. PIN CONFIGURATION DESCRIPTION The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs. BLOCK DIAGRAM 1 2 3 4 5 6 7 8 XIN/FIN GND CLK0 XOUT DNC VDD 1 2 3 4 5 6 7 8 CLK1 CLK2, OE, FSEL SOP-8 MSOP-8 Phase Detector Charge Pump Loop Filter VCO Xtal OSC XIN/FIN XOUT P-counter (5-bit) M-counter ( 6-bit) R-counter CLK[0:1] CLK2 FRef . OE FSEL FVCO = F Ref. * (2 * M /R) FOut = FVCO / (2 * P) CLoad Programmable Function /1, /2 |
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