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PLL102-108 Datasheet(PDF) 9 Page - PhaseLink Corporation |
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PLL102-108 Datasheet(HTML) 9 Page - PhaseLink Corporation |
9 / 10 page PLL102-108 Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 9 3. Recommended Operating Conditions PARAMETERS SYMBOL MIN. TYP. MAX. UNITS Output supply voltage VCC 2.3 2.5 2.7 V Analog Supply voltage ACC 2.3 2.5 2.7 V High level input voltage VIH 0.7 x VCC V Low level input voltage VIL 0.3 x VCC V Operating free-air temperature TA 0 70 °C 4. Timing requirements SYMBOL PARAMETERS MIN. MAX. UNITS FCLK Input clock frequency 66 266 MHz DIN Input clock duty cycle 40 60 % TS Stabilization time after power up 0.1 ms 5. Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Low to high level propagation delay time TPLH CLK_INT to any output 0 High to low level propagation delay time TPHL CLK_INT to any output 0 ns 66MHz 120 Jitter (peak to peak) Tp-p 100/133/200/266MHz 75 ps 66MHz 110 Jitter (cycle to cycle) Tcyc-cyc 100/133/200/266MHz 65 ps Phase error t(phase error) -150 150 Output to output skew Toskew 100 Pulse skew Tpskew All differential input and output terminals are terminated with 120 Ω/16pF 100 ps 66MHz to 100MHz 49.5 50.5 Duty Cycle DT 101MHz to 266MHz 49 51 % Rise time, Fall time tr, tf Load = 120 Ω/16pF 650 800 950 ps |
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