PLL102-108

Programmable DDR Zero Delay Clock Driver

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/29/02 Page 9

3. Recommended Operating Conditions

PARAMETERS

SYMBOL

MIN.

TYP.

MAX.

UNITS

Output supply voltage

2.3

2.5

2.7

V

Analog Supply voltage

2.3

2.5

2.7

V

High level input voltage

V

Low level input voltage

V

Operating free-air temperature

0

70

°C

4. Timing requirements

SYMBOL

PARAMETERS

MIN.

MAX.

UNITS

Input clock frequency

66

266

MHz

Input clock duty cycle

40

60

%

Stabilization time after power up

0.1

ms

5. Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Low to high level propagation

delay time

CLK_INT to any output

0

High to low level propagation

delay time

CLK_INT to any output

0

ns

66MHz

120

Jitter (peak to peak)

100/133/200/266MHz

75

ps

66MHz

110

Jitter (cycle to cycle)

100/133/200/266MHz

65

ps

Phase error

-150

150

Output to output skew

100

Pulse skew

All differential input and output

terminals are terminated with

120

Ω/16pF

100

ps

66MHz to 100MHz

49.5

50.5

Duty Cycle

101MHz to 266MHz

49

51

%

Rise time, Fall time

Load = 120

Ω/16pF

650

800

950

ps