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PLL103-02D Datasheet(PDF) 3 Page - PhaseLink Corporation |
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PLL103-02D Datasheet(HTML) 3 Page - PhaseLink Corporation |
3 / 7 page PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 3 I2C BUS CONFIGURATION SETTING Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Slave Receiver/Transmitter Provides both slave write and readback functionality Data Transfer Rate Standard mode at 100kbits/s Data Protocol This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 48 1 Reserved Bit 6 - 0 Reserved Bit 5 - 0 Enhanced DDR Drive. 1 = Enhanced 25% Bit 4 - 0 Reserved Bit 3 45, 44 1 DDR11T, DDR11C Bit 2 43, 42 1 DDR10T, DDR10C Bit 1 39, 38 1 DDR9T, DDR9C Bit 0 34, 33 1 DDR8T, DDR8C |
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