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PL680-38QC-R Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PL680-38QC-R Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 10 page (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1 FEATURES • Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies. • Less than 25ps peak to peak jitter for all frequencies. • Low phase noise output (@ 1MHz frequency offset ∗ -144dBc/Hz for 106.25MHz ∗ -144dBc/Hz for 156.25MHz ∗ -144dBc/Hz for 212.5MHz ∗ -140dBc/Hz for 312.5MHz, ∗ -131dBC/Hz for 622.08MHz • 19MHz-40MHz crystal input. • 38MHz-640MHz output. • Available in PECL, LVDS, or CMOS outputs. • Output Enable selector. • 2.5V & 3.3V operation. • Available in 3x3 QFN or 16-pin TSSOP packages. DESCRIPTION The PL680-3X is a monolithic low jitter and low phase noise high performance clock, capable of maintaining 0.4ps RMS phase jitter and CMOS, LVDS or PECL outputs, covering a wide frequency output range up to 640MHz. It allows high performance and high frequency output, using a low cost fundamental crystal of between 19-40MHz.. The frequency selector pads of PL680-3X enable output frequencies of (2, 4, 8, or 16) * FXIN. The PL680-3X is designed to address the demanding requirements of high performance applications such Fiber Channel, serial ATA, Ethernet, SAN, etc. PACKAGE PIN ASSIGNMENT 16-pin TSSOP 3x3 QFN Note1: QBAR is used for single ended CMOS output . Note2: ^ Denotes internal pull up resistor. BLOCK DIAGRAM 1 2 3 4 5 6 7 8 VDDANA 9 10 11 12 13 14 15 16 XIN XOUT SEL2^ OE_CTRL DNC GNDANA LP SEL0^ GNDBUF SEL1^ GNDBUF QBAR VDDBUF Q LM PL680-3X GNDBUF VDDBUF Q QBAR SEL2^ XOUT OE_CTRL DNC 4 16 15 14 13 12 11 10 9 8 7 6 5 12 3 Phase Detector Charge Pump Loop Filter VCO (FXiNx16) VCO Divider XTAL OSC QBAR OE XIN XOUT Q + Performance Tuner Output Divider (1,2,4,8) |
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Similar Description - PL680-38QC-R |
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