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PLL650-05ACLR Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL650-05ACLR Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 6 page PLL650-05 Low EMI Network LAN Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2 PIN DESCRIPTIONS Name Number Type Description XIN 1 I 25MHz fundamental crystal input (20pF CL parallel resonant). XOUT/ENB_125M 2 B Crystal output. At power-up, this pin latches ENB_125M (output enable selector for 125MHz output. Disabled when ENB_125M is logical zero. Has 120k Ω internal pull up resistor. 125MHz 5 O 125MHz output. 75MHz/FS1 7 B 75MHz output. This pin latch FS1 value at power-up. It has 60k Ω internal pull up resistors. ENB_75M 8 I Output enable for 75Mhz output when high. Disabled when ENB_75M is logical low. It has 60K Ω internal pull up resistor. SS0 9 I This pin is a tri-level input pin to control the spread spectrum function. See Spread Spectrum Selection Table SDRAMx2 11 O SDRAM outputs with double drive strength determined by FS(0:1) value. 25MHz/FS0 14 B 25MHz (reference) output. This pin latch FS0 value at power-up. It has 60k Ω internal pull up resistors. VDD 4,10,15,16 P Power supply. GND 3,6,12,13 P Ground. SPREAD SPECTRUM SELECTION TABLE SS0 SST 0 ±0.75% Center M OFF 1 ±0.5% Center FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies The PLL650-05 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by connecting specific pins to a logical “zero” or “one”, or by leaving them not connected (tri-level inputs or internal pull-up) according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively. In order to reduce pin usage, the PLL650-05 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 (Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to GND. Likewise, in order to connect to a logical “one” the pin must be connected to VDD. Connecting a bi-directional pin A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", |
Similar Part No. - PLL650-05ACLR |
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Similar Description - PLL650-05ACLR |
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