ICs for TV

AN5308NK

9

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Horizontal signal processing (continued)

F.B.P slice level (blanking)



0.7



V

F.B.P slice level (AFC1)



2.5



V

F.B.P delay time range



19

µs

edge to FBP center

B.G.P start position

From H. sync. rear edge to burst



0.3

µs

gate pulse front edge

Sandcastle pulse output temperature

∆V

60(Ta)



1.8

 mV/deg

characteristics

Sandcastle pulse input threshold

∆V

59(Ta)



0

 mV/deg

level temperature characteristics

F.B.P input threshold level

∆V

61(Ta)

−1.8

 mV/deg

temperature characteristics (HBLK)

F.B.P input threshold level



1

 mV/deg

temperature characteristics (AFC1)

X-ray inside reference temperature

Zener temperature characteristics:



0

 mV/deg

characteristics

+1.8 mV/deg

Sandcastle pulse output vs. supply



1



V/V

voltage dependence (BGP)

Sandcastle pulse output vs. supply



0.74



V/V

voltage (HBLK)

Sandcastle pulse output vs. supply



0.44



V/V

voltage (VBLK)

Hold down operation voltage

2.71

2.81

2.91

V

Vertical signal processing

Vertical BLK phase (wide)

PVBLK(W) Period from VBLK rising edge to



3.87



ms

vertical sync. falling edge

Vertical BLK phase (normal)

PVBLK

Period from VBLK rising edge to



0.2



ms

vertical sync. falling edge

Neck break operation pin 60 voltage

Pin 6: 1.5 V

1.5



V

Vertical BLK pulse width (wide)

TVBLK(W)



5.05



ms

Y-signal processing

Contrast variable range



40



dB

∆y



0.4



dB/V



0.18



V/V

Y-noise level



750

mV

Delay line dynamic range



0.7



V

• Design reference data (continued)

Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.