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PLL602-89CSC Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL602-89CSC Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 5 page PLL602-89C 12-27 MHz XO IC with 1 Pair of LVDS and 2 CMOS Outputs 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1 FEATURES • Low jitter XO for the 12MHz to 27MHz range. • Integrated crystal load capacitor: no external load capacitor required. • 1 pair of LVDS outputs and 2 CMOS outputs. • 12-27 MHz fundamental crystal input. • Low jitter (RMS): 2.5 ps period jitter (1 sigma). • 2.5V to 3.3V operation. • Available in 8-Pin SOIC package. PIN CONFIGURATION (Top View) DESCRIPTION The PLL602-89C is a high performance multiple output XO IC chip. It provides 1 pair of LVDS and 2 CMOS out- puts. The chip combines a crystal oscillator (XO) with a multiple-output buffer. It accepts a low cost fundamental parallel resonant mode crystal from 12MHz to 27MHz, which is reproduced at the outputs. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for data and telecommunication applications. BLOCK DIAGRAM 1 2 3 45 6 7 8 VDD XIN XOUT GND CMOS1_CLK LVDS_CLK CMOS2_CLK LVDSBAR_CLK XOUT LVDS_CLK XIN CMOS1_CLK Oscillator Amplifier CMOS2_CLK LVDSBAR_CLK (8 pin SOIC) |
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