11
P/N:PM1185
MX29LV008C T/B
REV. 1.0, JUN. 30, 2005
time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RESET# pin returns
to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 20 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The de-
vice remains enabled for reads until the command regis-
ter contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
The MX29LV008C T/B contains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 3EH for MX29LV008CT, 37H for MX29LV008CB.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H or
sector erase command 30H.
The Automatic Chip Erase does not require the device to
be entirely pre-programmed prior to executing the Auto-
matic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verify begin. The erase
and verify operations are completed when the data on
Q7 is "1" at which time the device returns to the Read
mode. The system is not required to provide any control
or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 7), indicating the erase operation ex-
ceed internal timing limit.
The automatic erase begins on the rising edge of the last
WE# or CE# pulse, whichever happens first in the com-
mand sequence and terminates when the data on Q7 is
"1" and the data on Q6 stops toggling for two consecu-
tive read cycles, at which time the device returns to the
Read mode.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
