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PLL520-28OC Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL520-28OC Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 7 page PLL520-28/-29 Low Phase Noise VCXO (for 120-200MHz Fund Xtal) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PIN DESCRIPTIONS Name TSSOP Pin number 3x3mm QFN Pin number Type Description XIN 2 13 I Crystal input. See Crystal Specifications on page 2. XOUT 3 14 I Crystal output. See Crystal Specifications on page 2. OE 6 16 I Output enable pin. See Output Enable Logic Levels on page 1. VCON 7 1 I Voltage control input. GND 8, 14 2,3,4,8 P Ground. CLKT 11 5 O True output PECL (PLL520-28) or LVDS (PLL520-29) CLKC 13 7 O Complementary output PECL (PLL520-28) or LVDS (PLL520-29). N/C 4,5,9,10,15,16 9,10,15 - Not connected. VDD 1, 12 6,11,12 P +3.3V power supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS CX+ 2 Built-in Capacitance CX- 2 Inter-electrode capacitance C0 120MHz to 200MHz (VDD=3.3V) 2 pF C0/C1 ratio (gamma) γ 300 - Oscillation Frequency OF Fund. 120 200 MHz |
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