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PLL620-3XOI Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL620-3XOI Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 6 page PLL620-38/39 PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 1 FEATURES • 65MHz to 130MHz Crystal input. • Output range: 32.5MHz – 130MHz (no PLL). • Low Injection Power for crystal, 50uW. • PECL (PLL620-38) or LVDS output (PLL620-39). • Supports 2.5V or 3.3V-Power Supply. • Available in 16-Pin TSSOP. DESCRIPTION The PLL620-38/-39 is a family of XO IC’s specifically designed to work with high frequency fundamental or 3rd OT crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs. They achieve very low current into the crystal resulting in better overall stability. Their very low jitter makes them ideal for the most demanding timing requirements. BLOCK DIAGRAM PIN CONFIGURATION Note: ^ designates internal pull-up resistor. OUTPUT ENABLE LOGICAL LEVELS Part # OE State 0 (Default) Output enabled PLL620-38 1 Tri-state 0 Tri-state PLL620-39 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL620-38 Logical states defined by CMOS levels for PLL620-39 OUTPUT FREQUENCY SELECTOR S2 Output 0 Input/2 1(Default)* Input *Internally set to ‘Default’ through 60K pull-up resistor ! XIN XOUT OE Q PLL620-38/-39 Q Oscillator Amplifier S2 |
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