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PLL600-27T-37T Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL600-27T-37T Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 4 page Preliminary PLL600-27T/-37T Low Power 3 Outputs XO 10MHz to 52MHz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 2 PIN DESCRIPTION Name Pin # Type Description XIN/FIN 1 I Crystal input ( 10MHz to 52MHz ) or Ref Clock input. OE 2 I Output Enable input. This pin has internal pull-up resistor. All outputs will be tri-stated when low. CLK1 3 O Output clock. GND 4 P Ground. CLK2 5 O Output clock. VDD 6 P Power supply. CLK0 7 O Output clock. XOUT 8 I Crystal output. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Electrical Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Crystal Frequency 10 52 MHz Settling time At power-up (Vdd reaches 1.62V) 10 ms 0.8V ~ 2.0V with 10 pF load 1.15 Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 2.4 ns VDD sensitivity Frequency vs. VDD +/- 10% 0.8 0.8 ppm Output Clock Duty Cycle Measured @ 50% VDD 45 50 55 % Short Circuit Current ±50 mA |
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