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P600-37SC Datasheet(PDF) 2 Page - PhaseLink Corporation

Part # P600-37SC
Description  Ultra Low Current XO 10 MHz to 52 MHz
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

P600-37SC Datasheet(HTML) 2 Page - PhaseLink Corporation

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Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 2
PIN/PAD DESCRIPTION
Pin #
Name
8 pin
SOIC
6 pin
SOT
Type
Description
XIN
1
4
I
Crystal input or reference clock input pin.
N/C
2
n/a
I
No connect.
GND
3
2
P
Ground.
OSCSEL
4
n/a
I
Disable mode select. See Table on page 1.
CLK
5
1
O
Output clock.
VDD
6
6
P
Power supply.
OE
7
5
I
Output Enable input. See Table on page 1.
XOUT
8
3
I
Crystal output.
OE and OSCSEL have internal pull-ups, so the default value is ‘1’ when not connected (OSCSEL not available on 6 pin package).
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
4.6
V
Input Voltage, dc
VI
-0.5
VDD+0.5
V
Output Voltage, dc
VO
-0.5
VDD+0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
-40
85
°C
Junction Temperature
TJ
125
°C
Lead Temperature (soldering, 10s)
260
°C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Crystal Frequency
10
52
MHz
At power-up
(Vdd reaches 1.62V)
10
ms
Disable to enable, osc. Off
10
ms
Settling time
Disable to enable, osc. On
500
µs
0.8V ~ 2.0V with 10 pF load
1.15
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
2.4
ns
VDD sensitivity
Frequency vs. VDD +/- 10%
0.8
0.8
ppm
Output Clock Duty Cycle
Measured @ 50% VDD
45
50
55
%


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