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PLL701-05 Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL701-05 Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 5 page Preliminary PLL701-05 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/26/02 Page 2 BLOCK DIAGRAM PIN DESCRIPTIONS Name Number Type Description FIN 1 I Input Clock Frequency. S0 2 I Digital control input to select output frequency. Has internal pull-up. S1 3 I Digital control input to select output frequency. Has internal pull-up. S2 4 I Digital control input to select output frequency. Has internal pull-down. S3 7 I Digital control input to select output frequency. Has internal pull-down. VDD 8 P 3.3V Power Supply. FOUT 6 O Modulated Clock Frequency Output. The frequency before modulation is synthesized by multiplying the input frequency by 1X, 2X, or 4X, depending on S(0:3). GND 5 P Ground. XTAL OSC FOUT XIN XOUT S(0:3) PLL SST Control Logic VDD |
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