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PLL701-10 Datasheet(PDF) 4 Page - PhaseLink Corporation |
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PLL701-10 Datasheet(HTML) 4 Page - PhaseLink Corporation |
4 / 8 page PLL701-10 Low EMI Spread Spectrum Multiplier IC (in Die or Package) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 FUNCTIONAL DESCRIPTION Selectable spread spectrum and modulation rates The PLL701-10 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation, as well as selectable modulation rate. Selection is made by connecting specific input pins to a logical “zero” or “one”. Pins 6 (SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation as shown on the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as inputs to select the output frequency as shown on the output clock selection table (page 1). Pin 11 is the output enable pin, that tri-states all outputs when low (logical “zero”). In order to reduce the number of pins on the chip, the PLL701-10 uses pin 2 and 14 (XOUT/SD0 and REF/SD1) as a bi-directional pin. The pins serve as modulation rate selector inputs (SD0 and SD1) upon power-up (see modulation rate table on page 1), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon as the inputs have been latched. Connecting a selection pin to a logical “one” All selection pins have an internal pull-up resistor (30k Ω for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120kΩ for pin 2). This internal pull-up resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a logical “one” upon power-up. Connecting a selection pin to a logical “zero” For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be grounded to pull the input down to a logical “zero”. Connecting the bi-directional pins (SD0 and SD1) to a logical “zero” will however require the use of an external loading resistor between the pin and GND that has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around Rup/4 (e.g. 27k Ω for pin 2 and 4.7kΩ for pin 14, see Application Diagram). APPLICATION DIAGRAM FOR OUTPUT AND MODULATION SELECTION Latch Power Up Reset Jumper options R up/4 Clock Load SD0 or SC0~SC2 XIN EN VDD R up Bi-directional pin R RB NOTE: Rup=120k Ω for SD0 (Pin2); and Rup=30kΩ for SD1(Pin 14). R starts from 1 to 0 while RB starts from 0 to 1. Internal to chip External Circuitry |
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