Electronic Components Datasheet Search |
|
PLL701-11SCL Datasheet(PDF) 2 Page - PhaseLink Corporation |
|
PLL701-11SCL Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 5 page PLL701-11 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/17/06 Page 2 BLOCK DIAGRAM PIN DESCRIPTIONS Name Number Type Description FIN 1 I Input Clock Frequency, 24MHz to 120MHz. S2 2 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-up. S1 3 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-up. S0 4 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-down. GND 5 P Ground. FOUT 6 O SST Modulated Clock Frequency Output. The frequency before modulation is synthesized by multiplying the input frequency by 1X, 2X, or 4X, depending on S(0:3). S3 7 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-down. VDD 8 P 3.3V Power Supply. FOUT FIN S(0:3) PLL SST Control Logic |
Similar Part No. - PLL701-11SCL |
|
Similar Description - PLL701-11SCL |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |