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P702-01XC Datasheet(PDF) 1 Page - PhaseLink Corporation |
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P702-01XC Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 8 page PLL702-01 Clock Generator for PowerPC Based Applications 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/05 Page 1 FEATURES • 1 CPU Clock output with selectable frequencies (50, 66, 75, 80, 83, 90, 100,125 or 133 MHz). • 1 ASIC output clock (at CPU clock or CPU clock ÷ 2). • 2 ASIC output clocks (at CPU clock) w/ output enable. • 1 PCI output clock w/ output enable • 1 Selectable 48, 30 or 12MHz (USB) output. • Selectable Spread Spectrum (SST) for EMI reduction on ASIC and CPU. • PowerPC compatible output and drive CPU Clock. • Selectable reduced 67% drive strength on CPU Clock • Advanced, low power, sub-micron CMOS processes. • 14.31818MHz fundamental crystal input. • 3.3V and/or 2.5V operation. • Available in 28-Pin 209mil SSOP (QSOP). DESCRIPTION The PLL702-01 is a low cost, low jitter, and high performance clock synthesizer for generic PowerPC based applications. It provides one CPU clock, three ASIC outputs, one PCI output, and a selectable 48, 30 or 12MHz (USB) output. The user can choose between 9 different CPU clock frequencies, while the ASIC output can be identical or half of the CPU frequency. Low EMI Spread Spectrum Technology is available for the CPU, ASIC and PCI clocks. The CPU drive strength is user selectable from 100% to 67%. All frequencies are generated from a single low cost 14.31818MHz crystal. The CPU and ASIC clock can be driven from an independent 2.5V power supply. PIN ASSIGNMENT (28 pin SSOP) FREQUENCY TABLES ASIC1 (MHz) PCI* (MHz) CLK_SEL1 CLK_SEL0 CPU (MHz) ASIC1_SEL =1 ASIC1_SEL =0 ASIC2 (MHz) PCI_SEL =0 PCI_SEL =M 0 0 50 50 25 50 62.5 31.25 0 M 66 66 33 66 66.7 33.35 0 1 75 75 37.5 75 62.5 31.25 M 0 80 80 40 80 66.7 33.35 M M 83 83 41.5 83 66.7 33.35 M 1 90 90 45 90 66.7 33.35 1 0 100 100 50 100 66.7 33.35 1 M 125 125 62.5 125 62.5 31.25 1 1 133 133 66.5 133 65.5 32.75 Notes: When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification. * PCI_SEL=1 sets the Tri-state (output disabled) mode of the output. BLOCK DIAGRAM XTAL OSC XIN XOUT SSC(0:1) PLL SST Control Logic CPU_CLK PLL Control Logic USB_SEL CLK_SEL(0:1) ASIC1 DIV 2 USB ASIC1_SEL PCI_SEL ASIC2(A:B) PCI PCI_OE ASIC2_OE ^: Internal pull-up resistor *: Bi-directional pin o : Selectable reduced drive strength T : Tri-level input 28 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 22 21 20 19 18 17 16 15 XIN VDD_ANA XOUT / ASIC2_OE*^ VDD_DIG SSCO^ SSC1^ GND_ANA VDD_PCI PCI / PCI_SEL*T GND_USB GND_PCI VDD_USB USB / USB_SEL*T VDD_ASIC2 Note : ASIC2A ASIC2B CLK_SEL0T CLK_SEL1T GND_CPU U CP o VDD_CPU VDD_ASIC1 ASIC1 GND_ASIC1 GND_ASIC2 GND_DIG ASIC1_SEL^ CPUDRV_SEL^ |
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