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PLL701-17SIL Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL701-17SIL Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 5 page PLL701-17 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/17/06 Page 2 BLOCK DIAGRAM PIN DESCRIPTIONS Name Number Type Description FIN 1 I Input Clock connection. 16MHz to 60MHz. S2 2 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-up. S1 3 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-up. S0 4 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-down. GND 5 P Ground connection. FOUT 6 O SST Modulated Clock Output. The frequency before modulation is synthesized by multiplying the input frequency by 1X, 2X, 2.94Xor 4X, depending on S(0:3). S3 7 I Digital control input to select multiplication factor and SST modulation amplitude. Has internal pull-down. VDD 8 P 3.3V Power Supply connection. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. FOUT FIN S(0:3) PLL SST Control Logic |
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