PLL130-09

High Speed Translator Buffer to LVDS

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

FEATURES

• Differential LVDS output

• Single AC coupled input (min. 100mV swing).

• Input range from DC to 1.0 GHz.

• 2.5V to 3.3V operation.

• Available in 8-Pin SOIC or 3x3mm QFN.

DESCRIPTION

The PLL130-09 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.0GHz. It provides a pair of

differential LVDS output. Any input signal with at

least 100mV swing can be used as reference

signal. This chip is ideal for conversion from sine

wave, TTL, CMOS, or PECL to LVDS.

PIN CONFIGURATION

(TOP VIEW)

BLOCK DIAGRAM

Input

Amplifier

LVDS_BAR

REF_IN

LVDS

1

2

3

45

6

7

8

GND

REF_IN

GND

LVDS

VDD

LVDS_BAR

VDD

GND

PLL130-09

LVDS_BAR

LVDS

GND

VDD

12

3

4

12

11

10

9

13

14

15

16

8

7

6

5

GND

GND

GND

OE^

Note: ^ denotes internal pull up