PLL500-27/-37/-47

Low Power CMOS Output VCXO Family (27MHz to 200MHz)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/21/04 Page 1

FEATURES

• VCXO output for the 27MHz to 200MHz range

-

PLL500-27: 27MHz to 65MHz

-

PLL500-37: 65MHz to 130MHz

-

PLL500-47: 100MHz to 200MHz

• Low phase noise (-130 dBc @ 10kHz offset).

• CMOS output with OE tri-state control.

• Selectable output drive (Standard or High drive).

-

Standard: 12mA drive capability at TTL level.

-

High: 36mA drive capability at TTL level.

• Fundamental crystal input.

• Integrated high linearity variable capacitors.

• +/- 150 ppm pull range, max 5% linearity.

• Low jitter (RMS): 2.5ps period jitter.

• 2.5-3.3V operation.

• Available in 8-Pin SOIC or DIE.

DESCRIPTION

The PLL500-27/-37/-47 are a low cost, high perform-

ance, low phase noise, and high linearity VCXO fam-

ily for the 27 to 200MHz range, providing less than -

130dBc at 10kHz offset. The very low jitter (2.5 ps

RMS period jitter) makes these chips ideal for appli-

cations requiring voltage controlled frequency

sources. The IC’s are designed to accept fundamen-

tal resonant mode crystals.

PIN CONFIGURATION

DIE PAD LAYOUT

FREQUENCY RANGE

PART #

MULTIPLIER

FREQUENCY

PLL500-27

No PLL

27 – 65 MHz

PLL500-37

No PLL

65 – 130 MHz

PLL500-47

No PLL

100 – 200 MHz

BLOCK DIAGRAM

XTAL

OSC

OE

XIN

XOUT

VCON

VARICAP

1

2

3

4

5

6

7

8

XIN

DRIVSEL^

VCON

GND

XOUT

VDD

CLK

OE^

^: Denotes internal Pull-up

1

2

3

4

7

6

5

8