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PLL500-37B Datasheet(PDF) 3 Page - PhaseLink Corporation |
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PLL500-37B Datasheet(HTML) 3 Page - PhaseLink Corporation |
3 / 5 page PLL500-27B/-37B/-47B Low Power CMOS Output VCXO Family (27MHz to 200MHz) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/13/04 Page 3 2. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS PLL500-27 27 65 PLL500-37 65 130 Input Crystal Frequency PLL500-47 100 200 MHz 0.8V ~ 2.0V with 10 pF load 1.15 Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 3.7 ns Output Clock Duty Cycle Measured @ 1.4V 45 50 55 % Short Circuit Current ±50 mA 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid 10 ms VCXO Tuning Range XTAL C0/C1 < 250 300 ppm CLK output pullability 0V ≤ VCON ≤ 3.3V ±150 ppm VCXO Tuning Characteristic 100 ppm/V Pull range linearity 5 % Power Supply Rejection PWSRR Frequency change with VDD varied +/- 10% -1 +1 ppm VCON pin input impedance 2000 k Ω VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 45 kHz Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS RMS Period Jitter (1 sigma – 1000 samples) With capacitive decoupling between VDD and GND. 2.5 ps Phase Noise relative to carrier @100Hz offset -80 dBc/Hz Phase Noise relative to carrier @1kHz offset -110 dBc/Hz Phase Noise relative to carrier @10kHz offset -130 dBc/Hz Phase Noise relative to carrier @100kHz offset -138 dBc/Hz Phase Noise relative to carrier @1MHz offset -145 dBc/Hz |
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