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PLL500-37BSCL Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL500-37BSCL Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 5 page PLL500-17B/27B/37B Low Power CMOS Output VCXO Family (17MHz to 130MHz) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 1 FEATURES • VCXO output for the 17MHz to 130MHz range - PLL500-17B: 17MHz to 36MHz - PLL500-27B: 27MHz to 65MHz - PLL500-37B: 65MHz to 130MHz • Low phase noise (-142 dBc @ 10kHz offset). • CMOS output with OE tri-state control. • Selectable output drive (Standard or High drive). - Standard: 8mA drive capability at TTL level. - High: 24mA drive capability at TTL level. • Fundamental crystal input. • Integrated high linearity variable capacitors. • +/- 150 ppm pull range, max 5% linearity. • Low jitter (RMS): 2.5ps period jitter. • 2.5 to 3.3V operation. • Available in 8-Pin SOIC or DIE. DESCRIPTION The PLL500-17B/27B/37B are a low cost, high per- formance, low phase noise, and high linearity VCXO family for the 17 to 130MHz range, providing less than -130dBc at 10kHz offset. The very low jitter (2.5 ps RMS period jitter) makes these chips ideal for applications requiring voltage controlled frequency sources. The IC’s are designed to accept fundamen- tal resonant mode crystals. FREQUENCY RANGE PART # MULTIPLIER FREQUENCY PLL500-17B No PLL 17 – 36 MHz PLL500-27B No PLL 27 – 65 MHz PLL500-37B No PLL 65 – 130 MHz PIN CONFIGURATION ^: Denotes internal Pull-up DIE PAD LAYOUT DIE SPECIFICATIONS Name Value Size 39 x 32 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil BLOCK DIAGRAM XTAL OSC OE XIN XOUT VCON VARICAP 1 2 3 45 6 7 8 XIN OE^ VIN GND XOUT VDD* CLK DS^ 5 Y X (0,0) (812,986) 32 mil 8 6 2 3 4 7 DIE ID:PLL500-17B: C500A0505-05P PLL500-27B: C500A0505-05Q PLL500-37B: C500A0505-05R 1 XIN OE^ CLK GND VCON XOUT DRIVSEL^ VDD Note: ^ denotes internal pull up |
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