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ICSSSTVA16859BGLF-T Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICSSSTVA16859BGLF-T Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 11 page ICSSSTVA16859B 1050A—01/07/05 Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA. 3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz, Zo=50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd CL = 30 pF (see Note 1) From Output Under Test Load Circuit 1k Ω LVCMOS RESET# Input LVCMOS RESET# Input V DDQ /2 V DDQ /2 tinact tact I (see note 2) DD IDDH IDDL 10% 90% Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Propagation Delay Times Figure 1 - Parameter Measurement Information (V DDQ = 2.5V ±0.2V) Voltage Waveforms - Pulse Duration Voltage Waveforms - Setup and Hold Times VDDQ 0V t w t S t h VIH VIH VOH VTT VTT VTT VOH VIH VIL VIL VOL VOL VI(pp) VI(pp) VIL VREF VREF VREF VREF VICR VICR tPHL tPHL tPHL V/2 DD VICR Input Input Timing Input Timing Input Output Output 1k Ω Test point VDD |
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