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ICS1893AGLF Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS1893AGLF Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 135 page  ICS1893AG, Rev. A 04/14/05 April, 2005 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Integrated Circuit Systems, Inc. 3.3 V 10Base-T/100Base-TX Integrated PHYceiver ™ ICS1893AG Document Type: Data Sheet Document Stage: Preliminary Features • Single 3.3 V ±10% power supply • Supports category 5 cables with attenuation in excess of 24dB at 100 MHz across a temperature range from 0°C to +70°C. Industrial temperature version is also available. • DSP-based baseline wander correction to virtually eliminate killer packets • Low-power, 0.35-micron CMOS (typically 400 mW) • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard • 10Base-T and 100Base-TX IEEE 802.3 compliant • Clock or crystal supported • Media Independent Interface (MII) supported • Managed or Unmanaged Applications • 10M or 100M Half and Full Duplex Modes • Auto-Negotiation with Next Page. Parallel detection for Legacy products • Fully integrated, DSP-based PMD includes: – Adaptive equalization and baseline wander correction – Transmit wave shaping and stream cipher scrambler – MLT-3 encoder and NRZ/NRZI encoder • Loopback mode for Diagnostic Functions • Small footprint 56-pin 240 mil TSSOP package. General The ICS1893AG is a re-packaged version of the ICS1893AF in a 56-lead TSSOP 240 mil package. The ICS1893AG is a fully integrated, Physical Layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The ICS1893AG uses the same proven silicon as the ICS1893AF but offers a smaller form factor solution to users where physical package size is important. All parametric specification and timing diagrams for the ICS1893AF apply to the ICS1893AG. Refer to the ICS1893AF datasheet for detailed specifications and timing. The ICS1893AG uses the same twisted-pair transmit and receive circuits as the ICS1893AF, and the same recommended board layout techniques apply to the ICS1893AG. The ICS1893AG is intended for Node applications using the standard MII interface to the MAC. Clock Power LEDs and PHY Address Twisted- Pair Interface to Magnetics Modules and RJ45 Connector Integrated Switch MII Extended Register Set Interface MUX ICS1893AG Block Diagram PCS • Framer • CRS/COL Detection • Parallel to Serial •4B/5B Auto- Negotiation 10Base-T 100Base-TX TP_PMD •MLT-3 • Stream Cipher • Adaptive Equalizer • Baseline Wander Correction PMA • Clock Recovery • Link Monitor • Signal Detection • Error Detection Low-Jitter Clock Synthesizer Configuration and Status 10/100 MII MAC Interface MII Management Interface |
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