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ICS527R-03T Datasheet(PDF) 4 Page - Integrated Circuit Systems

Part # ICS527R-03T
Description  Clock Slicer User Configurable PECL Output Zero Delay Buffer
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS527R-03T Datasheet(HTML) 4 Page - Integrated Circuit Systems

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Clock Slicer User Configurable PECL Output Zero Delay Buffer
MDS 527-03 B
4
Revision 122804
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Prel iminar y Inf o r m ation
ICS527-03
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the right.
Note: The series termination resistor is located before
the feedback
F6
FBPECL
F5
F4
GND
F3
CLKIN
PDTS
F0
F1
F2
PECL
PECL
GND
S1
VDD
R0
VDD
DIV2
S0
R2
R1
R5
R6
R4
R3
FBPECL
RES
0.01 F
0.01 F
VDD
560
50 MHz
PECL output resistor network is not shown, but
is identical to PECL
VDD
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL


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