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ICS557G-08LF Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS557G-08LF Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 11 page MDS 557-08 C 2 Revision 021606 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com ICS557-08 2:1 Multiplexer Chip for PCI-Express Pin Assignment Select Table Pin Descriptions 1 2 3 IN2 4 IN1 5 6 GND 7 8 GND VDD SEL IN2 IN1 16 PD GND CLK VDD 15 14 13 12 11 10 9 16-pin (173 mil) TSSOP OE VDD IREF CLK SEL Input Pair selected 0IN2/ IN2 1IN1/ IN1 Pin Pin Name Pin Type Pin Description 1 VDD Power Connect to +3.3 V. Supply voltage for Input clocks. 2 IN1 Input HCSL/LVDS true input signal 1. 3IN1 Input HCSL/LVDS complimentary input signal 1. 4PD Input Powers down the chip and tri-states outputs when low. Internal pull-up resistor. 5 IN2 Input HCSL/LVDS true input signal 2. 6IN2 Input HCSL/LVDS complimentary input signal 2. 7 OE Input Provides output or, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor. 8 GND Power Connect to ground. 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 10 VDD Power Connect to +3.3 V. Supply Voltage for Output Clocks. 11 VDD Power Connect to +3.3 V. Supply Voltage for Output Clocks. 12 GND Power Connect to ground. 13 GND Power Connect to ground. 14 CLK Output HCSL/LVDS Complimentary output clock . 15 CLK Output HCSL/LVDS True output clock. 16 SEL Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. |
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