ICS558G-01LF datasheet(1/5 Pages) ICST

Part #	ICS558G-01LF

Description	PECL/CMOS TO CMOS CLOCK DIVIDER

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Manufacturer	ICST [Integrated Circuit Systems]

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ICS558-01

MDS 558-01 C

1

Revision 122105

Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m

PECL/CMOS TO CMOS CLOCK DIVIDER

Description

The ICS558-01 accepts a high speed input of either

PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and

provides four CMOS low skew outputs. The chip also

has output enables so that one, three, or all four

outputs can be tri-stated.

The ICS558-01 is a member of the ICS Clock Blocks™

family of clock generation, synchronization, and

distribution devices.

Features

• 16-pin TSSOP package

• Available in Pb (lead) free package

• Selectable PECL or CMOS inputs

• Operates up to 250 MHz

• Works as a voltage translator

• Four low skew (<250 ps) outputs

• Selectable internal divider

• Operating input voltages of 3.3 V or 5.0 V

• Operating output voltages of 2.5 V, 3.3 V or 5.0 V

• Ideal for IA64 designs

Block Diagram

OE1

CLK1

CLK2

CLK3

CLK4

PECLIN

Output Divide

PECLIN

S0, S1

GND

VDDP

OE0

GND

VDDC

2

1

0

CMOSIN

SELPECL

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