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ICS8430DY-111 Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS8430DY-111
Description  700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8430DY-111 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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8430DY-111
www.icst.com/products/hiperclocks.html
REV. F JUNE 1, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MHZ, LOW JITTER
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8430-111 is a general purpose, dual out-
put high frequency synthesizer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input lev-
els. The single ended TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL levels.
The VCO operates at a frequency range of 200MHz to 700MHz.
With the output configured to divide the VCO frequency by 2,
output frequency steps as small as 2MHz can be achieved
using a 16MHz differential or single ended reference clock. Out-
put frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-111 makes it an ideal
clock generator for most clock tree applications.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
• Dual differential 3.3V LVPECL output
• Selectable 14MHz to 27MHz differential CLK, nCLK
or TEST_CLK input
• CLK, nCLK accepts any differential input signal:
LVPECL, LVHSTL, LVDS, SSTL, HCSL
• TEST_CLK accepts the following input types:
LVCMOS, LVTTL
• Output frequency range up to 700MHz
• VCO range: 200MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial termperature information available upon request
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
÷ N
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
÷ 16
PHASE DETECTOR
÷ 2
HiPerClockS™
ICS
nCLK
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
N2
VEE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8430-111


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