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ICS8431I-21 Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICS8431I-21 Datasheet(HTML) 11 Page - Integrated Circuit Systems |
11 / 16 page 8431AMI-21 www.icst.com/products/hiperclocks.html REV. A AUGUST 2, 2005 11 Integrated Circuit Systems, Inc. ICS8431I-21 350MHZ, LOW JITTER, CRYSTAL OSCILLATOR- TO -3.3V LVPECL FREQUENCY SYNTHESIZER FIGURE 5B. PCB BOARD LAYOUT FOR ICS8431I-21 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C1, C2 and C6, as close as possible to the power pins. If space allows, placment of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin generated by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R5, C3, and C4 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The 50 Ω output trace pair should have same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in the example. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL_OUT) and 26 (XTAL_IN).The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted para- sitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C4 Signals X1 C3 VCC GND VIA C1 Zo=50 Ohm U1 Zo=50 Ohm C2 C8 R5 C6 ICS8431-21 C7 |
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