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ICS650GI-36 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS650GI-36 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 7 page Networking & PCI Clock Source MDS 650-36 D 5 Revision 030206 In te gr ated C i rcuit Syste m s ● 525 R ace Street, San Jose, CA 9 5126 ● tel (40 8) 29 7-120 1● www.icst.com ICS650-36 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 °C AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 °C Note 1: Measured with a 15 pF load. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.3 3.465 V Supply Current IDD No load, PDTS=1 25 mA Power Down Current IDDPD No load, PDTS=0 100 µA Input High Voltage VIH PDTS, S2:0 2 V Input Low Voltage VIL PDTS, S2:0 0.8 V Output High Voltage VOH IOH = -4 mA VDD-0.3 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA 0.4 V Short Circuit Current IOS Clock outputs ±65 mA Input Capacitance, inputs CIN 5pF Nominal Output Impedance ZOUT 20 Ω Internal Pull-up Resistor RPU PDTS, S2:0 500 k Ω Internal Pull-down Resistor RPD Outputs 250 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency fIN 25 MHz Output Rise Time tOR 20% to 80%, Note 1 0.8 ns Output Fall Time tOF 80% to 20%, Note 1 0.7 ns Output Clock Duty Cycle at VDD/2, Note 1 40 60 % Absolute Clock Period Jitter Note 1 ±125 ps Clock Jitter, Cycle-to-Cycle 33.333M, 66.666M, Note 1 150 ps Clock Jitter, Long Term 25M, n=1000, Note1 900 ps Frequency Synthesis Error 0 ppm Output Enable Time tOE PDTS high to output locked to ±1% 350 µs Output Disable Time tOD PDTS low to tri-state 25 ns |
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