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ICS8516FYI Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS8516FYI Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 13 page 8516FYI www.icst.com/products/hiperclocks.html REV. A JULY 30, 2004 8 Integrated Circuit Systems, Inc. ICS8516I LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP APPLICATION INFORMATION Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 2. In a 100 Ω dif- ferential transmission line environment, LVDS drivers require a matched load termination of 100 Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial out- puts are used, it is recommended to terminate the un-used outputs. FIGURE 2. TYPICAL LVDS DRIVER TERMINATION 3.3V R1 100 Zo = 50 Ohm LVDS_Driver HiPerClockS CLK nCLK Zo = 50 Ohm 3.3V V_REF R1 1K C1 0.1u R2 1K Single Ended Clock Input CLKx nCLKx VDD |
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