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ICS8521BYILF Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS8521BYILF
Description  LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8521BYILF Datasheet(HTML) 1 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
ICS8521I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8521BYI
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 17, 2005
1
PRELIMINARY
GENERAL DESCRIPTION
The ICS8521I is a low skew, 1-to-9 Differential-
to-HSTL Fanout Buffer and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8521I has two se-
lectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous asser tion/
deassertion of the clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521I ideal for today’s
most advanced applications, such as IA64 and static RAMs.
HiPerClockS™
ICS
FEATURES
• Nine HSTL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Output skew: 25ps (typical)
• Part-to-part skew: 200ps (typical)
• Propagation delay: 1.3ns (typical)
• V
OH = 1.4V (maximum)
• 3.3V core, 1.8V output operating supply voltages
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS
compliant packages
BLOCK DIAGRAM
PIN ASSIGNMENT
32 3 1 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
VDDO
ICS8521I
VDD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
D
Q
LE
CLK_EN
CLK_SEL
0
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.


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