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PE926C32 Datasheet(PDF) 2 Page - Peregrine Semiconductor Corp.

Part # PE926C32
Description  Quad RS-422 Differential Line Driver Radiation Hardened
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Manufacturer  PEREGRINE [Peregrine Semiconductor Corp.]
Direct Link  http://www.peregrine-semi.com
Logo PEREGRINE - Peregrine Semiconductor Corp.

PE926C32 Datasheet(HTML) 2 Page - Peregrine Semiconductor Corp.

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Product Specification
PE926C32
Page 2 of 6
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0158-01
│ UltraCMOS™ RFIC Solutions
Symbol
Parameter/Conditions
Min
Max
Units
V+
Supply voltage
3.0
3.6
V
TOP
Operating temperature
range
-55
125
°C
VIN (Line)
Maximum input voltage
A+/-, B+/-, C+/-, D+/-
-7
7
V
VIN (Dig)
Maximum input voltage
0
Vdd
V
VOUT
Maximum output voltage
0
Vdd
V
IOUT
Maximum output current
-10
10
mA
Pin
No.
Pin
Name
Description
1
A-
Channel A Inverting Input
2
A+
Channel A Noninverting Input
3
AQ
Channel A Output
4
E+
Enable, active high
5
BQ
Channel B Output
6
B+
Channel B Noninverting Input
7
B-
Channel B Inverting Input
8
V-
Ground Pin
9
C-
Channel C Inverting Input
10
C+
Channel C Noninverting Input
11
CQ
Channel C Ouput
12
E-
Enable, active low
13
DQ
Channel D Output
14
D+
Channel D Noninverting Input
15
D-
Channel D Inverting Input
16
V+
Supply Pin
1
A-
PE926C32
2
A+
3
AQ
4
E+
5
BQ
6
B+
7
B-
8
V-
16
15
14
13
12
11
10
9
V+
D-
D+
DQ
E-
CQ
C-
C+
Table 1. Pin Descriptions
Table 2. Recommended Operating Conditions
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 2.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Truth Table
Device Functional Considerations
The PE926C32 operates at high switching
speeds. In order to obtain maximum
performance, it is crucial that pin 16 be supplied
with a bypass capacitor to ground (pin 8).
Figure 2. Pin Configuration (Top View)
E+
E-
Vin (Diff)
Q
L
H
X
Z
H
X
<-200 mV
L
X
L
H
X
>+200 mV
H
X
L
H
X
Open
H
X
L


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