ICS85210-31 datasheet(3/14 Pages) ICST

Part #	ICS85210-31

Description	LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

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Manufacturer	ICST [Integrated Circuit Systems]

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3 / 14 page

85210AY-31

www.icst.com/products/hiperclocks.html

REV. B MARCH 19, 2004

3

Integrated

Circuit

Systems, Inc.

ICS85210-31

LOW SKEW, DUAL, 1-TO-5

DIFFERENTIAL-TO-HSTL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

TABLE 3B. CLOCK INPUT FUNCTION TABLE

s

t

u

p

n

Is

t

u

p

t

u

O

N

E

_

1

K

L

C

,

N

E

_

0

K

L

C4

B

Q

:

0

B

Q

,

4

A

Q

:

0

A

Q4

B

Q

n

:

0

B

Q

n

,

4

A

Q

:

0

A

Q

n

0W

O

L

;

d

e

l

b

a

s

i

DH

G

I

H

;

d

e

l

b

a

s

i

D

1d

e

l

b

a

n

Ed

e

l

b

a

n

E

e

g

d

e

k

c

o

l

c

t

u

p

n

i

g

n

il

l

a

f

d

n

a

g

n

i

s

i

r

a

g

n

i

w

o

ll

o

f

d

e

l

b

a

n

e

r

o

d

e

l

b

a

s

i

d

e

r

a

s

t

u

p

t

u

o

k

c

o

l

c

e

h

t

,

s

e

h

c

t

i

w

s

N

E

_

K

L

C

r

e

t

f

A

.

1

e

r

u

g

i

F

n

i

n

w

o

h

s

a

s

t

u

p

n

i

1

K

L

C

n

,

1

K

L

C

d

n

a

0

K

L

C

n

,

0

K

L

C

e

h

t

f

o

n

o

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n

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f

a

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a

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h

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d

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m

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a

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h

t

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I

.

B

3

e

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b

a

T

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d

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a

s

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p

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Is

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O

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M

t

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O

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u

p

n

Iy

t

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P

1

K

L

C

r

o

0

K

L

C1

K

L

C

n

r

o

0

K

L

C

n

,

4

A

Q

:

0

A

Q

4

B

Q

:

0

B

Q

,

4

A

Q

n

:

0

A

Q

n

4

B

Q

n

:

0

B

Q

n

00

W

O

LH

G

I

Hl

a

i

t

n

e

r

e

f

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D

o

t

l

a

i

t

n

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r

e

f

i

Dg

n

i

t

r

e

v

n

I

n

o

N

11

H

G

I

HW

O

Ll

a

i

t

n

e

r

e

f

i

D

o

t

l

a

i

t

n

e

r

e

f

i

Dg

n

i

t

r

e

v

n

I

n

o

N

01

E

T

O

N

;

d

e

s

a

i

BW

O

LH

G

I

Hl

a

i

t

n

e

r

e

f

i

D

o

t

d

e

d

n

E

e

l

g

n

i

Sg

n

i

t

r

e

v

n

I

n

o

N

11

E

T

O

N

;

d

e

s

a

i

BH

G

I

HW

O

Ll

a

i

t

n

e

r

e

f

i

D

o

t

d

e

d

n

E

e

l

g

n

i

Sg

n

i

t

r

e

v

n

I

n

o

N

1

E

T

O

N

;

d

e

s

a

i

B0

H

G

I

HW

O

Ll

a

i

t

n

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r

e

f

i

D

o

t

d

e

d

n

E

e

l

g

n

i

Sg

n

i

t

r

e

v

n

I

1

E

T

O

N

;

d

e

s

a

i

B1

W

O

LH

G

I

Hl

a

i

t

n

e

r

e

f

i

D

o

t

d

e

d

n

E

e

l

g

n

i

Sg

n

i

t

r

e

v

n

I

.

"

s

l

e

v

e

L

d

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d

n

E

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l

g

n

i

S

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p

e

c

A

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D

e

h

t

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r

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W

"

,

n

o

i

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p

A

e

h

t

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t

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e

f

e

r

e

s

a

e

l

P

:

1

E

T

O

N

FIGURE 1. CLK_EN TIMING DIAGRAM

Enabled

Disabled

nCLK0, nCLK1

CLK0, CLK1

CLK0_EN,

CLK1_EN

nQA0:nQA4,

nQB0:nQB4

QA0:QA4,

QB0:QB4

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