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PA7536JI-15 Datasheet(PDF) 3 Page - Anachip Corp |
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PA7536JI-15 Datasheet(HTML) 3 Page - Anachip Corp |
3 / 10 page 3 04-02-052A Sum-A = D, T, J or Sum-A Sum-B = Preset, K or Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable, Sum-D D R P Q D Re g is te r Q = D after clocked Best for storage, sim ple counters, shifters and state m achines with few hold (loop) conditions. T R P Q T R e gis te r Q toggles when T = 1 Q holds when T = 0 Best for wide binary counters (saves product term s) and state m achines with m any hold (loop) conditions. JK R e g ister Q toggles when J/K = 1/1 Q holds when J/K = 0/0 Q = 1 when J/K = 1/0 Q = 0 when J/K = 0/1 Com bines features of both D and T registers. J R P Q K 08-16-005A Figure 5. LCC Register Types SUM-A can serve as the D, T, or J input of the register or a combinatorial path. SUM-B can serve as the K input, or the preset to the register, or a combinatorial path. SUM-C can be the clock, the reset to the register, or a combinatorial path. SUM-D can be the clock to the register, the output enable for the connected I/O cell, or an internal feedback node. Note that the sums controlling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other PLDs. This also means that any input or I/O pin can be used as a clock or other control function. Several signals from the global cell are provided primarily for synchronous (global) register control. The global cell signals are routed to all LCCs. These signals include a high-speed clock of positive or negative polarity, global preset and reset, and a special register-type control that selectively allows dynamic switching of register type. This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from D-type registers to load and T-type registers to count (see Figure 11). Multiple Outputs Per Logic Cell An important feature of the logic control cell is its capability to have multiple output functions per cell, each operating independently. As shown in Figure 4, two of the three outputs can select the Q output from the register or the Sum A, B or C combinatorial paths. Thus, one LCC output can be registered, one output can be combinatorial and the third, an output enable or an additional buried logic function. The multi-function PEEL™ Array logic cells are equivalent to two or three macrocells of other PLDs, which have only one output per cell. They also allow registers to be truly buried from I/O pins without limiting them to input- only (see Figure 8 and Figure 9). I/O Cell (IOC) Input Cell (INC) REG/ Latch Q MUX Input To Array Input Cell Clock From Global Cell MUX From Logic Control Cell A,B,C or Q MUX MUX 1 0 D I/O Pin MUX To Array REG/ Latch Q Input Cell Clock From Global Cell Input Input 08-16-006A Figure 6. I/O Cell Block Diagram IO C/INC Re g is te r Q = D after rising edge of clock holds until next rising edge IO C /IN C L a tc h Q = L when clock is high holds value when clock is low LQ D Q 08-16-007A Figure 7. IOC Register Configurations |
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