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ICS843002AGLFT Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS843002AGLFT Datasheet(HTML) 10 Page - Integrated Circuit Systems |
10 / 16 page 843002AG www.icst.com/products/hiperclocks.html REV. B MAY 6, 2005 10 Integrated Circuit Systems, Inc. ICS843002 FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE Figure 4A shows a schematic example of the ICS843002. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF FIGURE 4A. ICS843002 SCHEMATIC EXAMPLE parallel resonant 26.5625MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. FIGURE 4B. ICS843002 PC BOARD LAYOUT EXAMPLE C1 27pF VCC VCCO Zo = 50 Ohm R6 50 C6 0.1u C4 0.01u X1 26.5625 MHz VCC=3.3V 18pF To Logic Input pins C7 0.1u Zo = 50 Ohm RU1 1K To Logic Input pins C9 0.1u Set Logic Input to '1' VCCO=3.3V VCC VCC R5 50 U1 ICS843002 VCC VCCO RD2 1K VCCA R4 50 C3 10uF Zo = 50 Ohm RD1 Not Install R2 10 Set Logic Input to '0' Zo = 50 Ohm + - C8 0.1u R7 50 Logic Control Input Examples R9 50 C2 33pF R8 50 + - RU2 Not Install PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of ICS843002 P.C. board layout. The crystal X1 footprint shown in this example allows installa- tion of either surface mount HC49S or through-hole HC49 pack- age.The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE e c n e r e f e Re z i S 2 C , 1 C2 0 4 0 3 C5 0 8 0 8 C , 7 C , 6 C , 5 C , 4 C3 0 6 0 2 R3 0 6 0 s e z i s t n e n o p m o c s t s il , 6 e l b a T : E T O N . e l p m a x e t u o y a l s i h t n i n w o h s |
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