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ICS843034AY-01 Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS843034AY-01 Datasheet(HTML) 3 Page - Integrated Circuit Systems |
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3 / 22 page  843034AY-01 www.icst.com/products/hiperclocks.html REV. C NOVEMBER 28, 2005 3 Integrated Circuit Systems, Inc. ICS843034-01 FEMTOCLOCKS™ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER PRELIMINARY Nx bits can be hardwired to set the M divider and Nx output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO fre- quency, the crystal frequency and the M divider is defined as follows: The M value and the required values of M0 through M5 are shown in Table 3B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 20 ≤ M ≤ 25. The frequency out is de- fined as follows: Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and Nx output di- vider when S_LOAD transitions from LOW-to-HIGH. The M divide and Nx output divide values are latched on the HIGH- to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and Nx output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and Nx bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes op- eration using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the In- put Frequency Characteristics, Table 5, NOTE 1. The ICS843034-01 features a fully integrated PLL and there- fore requires no external components for setting the loop band- width. A fundamental crystal is used as the input to the on- chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 490MHz to 640MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output fre- quency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers.The divider provides a 50% output duty cycle. The ICS843034-01 supports either serial or parallel program- ming modes to program the M feedback divider and N output divider.The input divider P can only be changed using the P_DIV pin. It cannot be changed from the default ÷1 setting using the serial interface. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on the M, NA, and NB inputs are passed directly to the M di- vider and both N output dividers. On the LOW-to-HIGH transi- tion of the nP_LOAD input, the data is latched and the M and N dividers remain loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Output 1 0 Output of M divider 1 1 CMOS Fout A0 FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS T 1 T0 NB2 NB1 NB0 NA2 NA1 NA0 M8 M7 M6 M5 M4 M3 M2 M1 M 0 S_CLOCK S_DATA S_LOAD nP_LOAD M0:M8, P_DIV, NA0:NA2, NB0:NB2 nP_LOAD fVCO = fxtal x M P FOUT = fVCO = fxtal x M NN x P SERIAL LOADING PARALLEL LOADING M, N, P t S t S t H t S t H Time S_LOAD |
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