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ICS843081AGI-01 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS843081AGI-01 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 15 page 843081AGI-01 www.icst.com/products/hiperclocks.html REV. B JANUARY 23, 2006 8 Integrated Circuit Systems, Inc. ICS843081I-01 FEMTOCLOCKS™CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK MULTIPLIER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed FIGURE 3B. LVPECL OUTPUT TERMINATION FIGURE 3A. LVPECL OUTPUT TERMINATION to drive 50 Ω transmission lines. Matched impedance tech- niques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two dif- ferent layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be rec- ommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN |
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