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ICS843004AG-01T Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # ICS843004AG-01T
Description  FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS843004AG-01T Datasheet(HTML) 8 Page - Integrated Circuit Systems

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843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843004-01
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V
CCA.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10
V
CCA
10
µF
.01
µF
3.3V
.01
µF
V
CC
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC - 2V
50
50
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
designed to drive 50
Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distor tion.
Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.


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