ICS843101AGI-312LFT datasheet(2/17 Pages) ICST

Part #	ICS843101AGI-312LFT

Description	FEMTOCLOCKS??CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

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843101AGI-312

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 1, 2005

2

Integrated

Circuit

Systems, Inc.

ICS843101I-312

FEMTOCLOCKS™CRYSTAL-TO-LVPECL

312.5MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

FUNCTIONAL DESCRIPTION

The ICS843101I-312 features a fully integrated PLL and

therefore requires no external components for setting the

loop bandwidth. A 25MHz fundamental crystal is used as

the input to the on chip oscillator. The output of the osc-

illator is fed into the pre-divider. In frequency margining

mode, the 25MHz crystal frequency is divided by 2 and

a 12.5MHz reference frequency is applied to the phase

detector. The VCO of the PLL operates over a range of

560MHz to 690MHz. The output of the M divider is also

applied to the phase detector.

The default mode for the ICS843101I-312 is 312.5MHz

output frequency using a 25MHz crystal. The output fre-

quency can be changed by placing the device into the

margining mode using the mode pin and using the serial

interface to program the M feedback divider. Frequency

margining mode operation occurs when the MODE input

is HIGH. The phase detector and the M divider force the

VCO output frequency to be M times the reference fre-

quency by adjusting the VCO control voltage. Note that for

some values of M (either too high or too low), the PLL will

not achieve lock. The output of the VCO is scaled by an

output divider prior to being sent to the LVPECL output

buffer. The divider provides a 50% output duty cycle. The

relationship between the crystal input frequency, the M

divider, the VCO frequency and the output frequency

is provided in Table 1. When changing back from fre-

quency margining mode to nominal mode, the device will

return to the default nominal configuration that will provide

312.5 MHz output frequency.

Serial operation occurs when S_LOAD is HIGH. Serial

data can be loaded in either the default mode or the fre-

quency margining mode. The 6-bit shift register is loaded

by sampling the S_DATA bits with the rising edge of

S_CLOCK. After shifting in the 6-bit M divider value,

S_LOAD is transitioned from HIGH to LOW which latches

the contents of the shift-register into the M divider control

register. When S_LOAD is LOW, any transitions of

S_CLOCK or S_DATA are ignored.

TABLE 1. FREQUENCY MARGIN FUNCTION TABLE

FIGURE 1. SERIAL LOAD OPERATIONS

Time

SERIAL LOADING

t

S

t

H

M5

M4

M3

M2

M1

M0

t

S

S_CLOCK

S_DATA

S_LOAD

L

A

T

X

)

z

H

M

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t

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M

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2

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2

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5

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2

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2

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1

0

1

15

.

7

8

62

5

7

.

3

4

30

.

0

1

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