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ICS671G-15T Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS671G-15T Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 6 page ICS671-15 MDS 671-15 B 1 Revision 021904 Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m ZERO DELAY, LOW SKEW BUFFER Description The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outputs running at 33 MHz, and two outputs at 66 MHz from the CPU PLL. This device also provides two 66 MHz zero delay clocks derived from the AGP PLL. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of the feedback clock. The ICS671-15 provides feedback clocks internally for the CPU PLL and the AGP PLL, and with the lowest jitter. Features • Packaged in 24-pin TSSOP • Input-output delay (±300 ps) • Two ZDB 66 MHz outputs from a 66 MHz input AGP clock • Two ZDB 66 MHz outputs, plus four 33 MHz outputs from a 33 MHz input CPU clock • Output-to-output skew is less than 250 ps • Full CMOS outputs with 18 mA output drive capability at TTL levels (at 3.3 V) • Spread SmartTM technology works with spread spectrum clock generators • Advanced, low-power, sub-micron CMOS process • Operating voltage of 3.3 V • Separate hardware output enable pins: OE1, OE2, OE3, OE4, OE5 and OE6 Block Diagram 66M_AGPOUT2 AGP PLL 66M_IN /2 VDD 4 GND 4 CPU PLL 33M_IN OE4 OE1 OE5 OE6 OE2 OE3 66M_AGPOUT1 66M_CPUOUT1 66M_CPUOUT2 33M_PCIOUT1 33M_PCIOUT2 33M_PCIOUT3 33M_PCIOUT4 |
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