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ICS843251AG-04T Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS843251AG-04T Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 10 page 843251AG-04 www.icst.com/products/hiperclocks.html REV. A SEPTEMBER 12, 2005 7 Integrated Circuit Systems, Inc. ICS843251-04 FEMTOCLOCKS™CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs.Therefore, terminat- ing resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3B. LVPECL OUTPUT TERMINATION FIGURE 3A. LVPECL OUTPUT TERMINATION drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN |
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