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ICS843404 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS843404 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 19 page  843404AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 17, 2005 1 Integrated Circuit Systems, Inc. ICS843404 LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR GENERAL DESCRIPTION The ICS843404 is a low phase noise Fibre Channel Clock Generator and is a member of the HiPerClockSTM family of high performance clock solutions from ICS. The device provides two banks of one LVPECL output per bank and one bank of two LVDS outputs. Each bank can be independently set by using their respective frequency select pins for the following output frequencies: 318.75MHz, 212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz 18pF parallel resonant crystal. The ICS843404 can also be driven from a 25.5MHz single-ended reference clock. For system debug or test purposes, the PLL can be bypassed using the VCO_SEL pin. FEATURES • Three banks of outputs: one bank of two LVDS outputs and two banks of one LVPECL output • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended reference clock input • Four independently selectable output frequency on each bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz • Maximum output frequency: 318.75MHz • Crystal input frequency: 25.5MHz •V DDO_LVPECL can be set for 3.3V or 2.5V, allowing the device to generate 3.3V or 2.5V LVPECL levels • RMS phase jitter at 106.25MHz, using a 25.5MHz crystal (637kHz to 10MHz intergration): 2.65ps (typical) Offset Noise Power 100Hz ................. -89.1 dBc/Hz 1kHz ................. -112.7 dBc/Hz 10kHz ................. -128.0 dBc/Hz 100kHz ................. -130.2 dBc/Hz • Supply voltage modes: • V DD = VDDA = 3.3V • V DDO_LVPECL = 3.3V or 2.5V • V DDO_LVDS = 3.3V • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages • Industrial termperature information available upon request HiPerClockS™ ICS PIN ASSIGNMENT 0 1 0 1 Phase Detector VCO 637.5MHz (Fixed) M = 25 (fixed) LVDS_FSEL1:0 0 0 ÷2 0 1 ÷3 1 0 ÷4 1 1 ÷6 LVPECL_FSELA1:0 0 0 ÷2 0 1 ÷3 1 0 ÷4 1 1 ÷6 LVPECL_FSELB1:0 0 0 ÷2 0 1 ÷3 1 0 ÷4 1 1 ÷6 25.5MHz V DDO_LVPECL V DDO_LVDS OSC BLOCK DIAGRAM VCO_SEL TEST_CLK XTAL_IN XTAL_OUT XTAL_SEL MR LVPECLA0 nLVPECLA0 LVPECLB0 nLVPECLB0 LVDS0 nLVDS0 LVDS1 nLVDS1 Pullup Pulldown Pullup Pulldown ICS843404 28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.92mm body package G Package Top View MR VCO_SEL VDDo_LVDS LVDS0 nLVDS0 LVDS1 nLVDS1 nc LVPECL_FSELB0 LVPECL_FSELB1 nc VDDA LVPECL_FSELA0 VDD LVDS_FSEL0 LVDS_FSEL1 VDDO_LVPECL LVPECLA0 nLVPECLA0 LVPECLB0 nLVPECLB0 XTAL_SEL TEST_CLK GND GND XTAL_IN XTAL_OUT LVPECL_FSELA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 |
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