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ICS844003AGI Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS844003AGI Datasheet(HTML) 10 Page - Integrated Circuit Systems |
10 / 13 page 844003AGI www.icst.com/products/hiperclocks.html REV. B AUGUST 25, 2005 10 Integrated Circuit Systems, Inc. ICS844003I FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER PRELIMINARY 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 Ω differential transmission line environment, LVDS drivers FIGURE 4. TYPICAL LVDS DRIVER TERMINATION require a matched load termination of 100 Ω across near the receiver input. R1 100 3.3V 100 Ohm Differential Transmission Line 3.3V + - LVDS INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100 Ω across. If they are left floating, we recommend that there is no trace attached. |
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