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W93910 Datasheet(PDF) 3 Page - Winbond |
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W93910 Datasheet(HTML) 3 Page - Winbond |
3 / 35 page W93910 Publication Release Date: Auguest 1999 - 3 - Revision A1 Pin Description, continued SYMBOL PIN I/O PIN DESCRIPTION TXCLK 12 I 192 option bits clock input from µC. TXDATA will be latched by W93910 during TXCLK rising edge. TXDATA 13 I/O 192 option bits serial data input from µC. Option bit address will be increased by one after each TXCLK period. After 192 option setting, the TXDATA pin will change to output pin for received OPID information access. ON 14 I Active high to enable W93910 chip operating. Oscillator starts oscillation after ON rising edge. OSCO will always stop while ON is low. XRST 15 I Internal pull low, Active high to reset decoder. PTEST 16 I Internal pull low, Test mode only. CHRS 17 I Force roaming control pin. Connect to GND for normal operation. Pull high is only for test purpose. XCNCG 18 O During PLEN pin high level, XCNCG (eXternal ChaNnel ChanGe) rising edge will inform µC to change channel according to channel scanning rule. SYNVAL 19 O Synchronization Indicator (out-of-range indicator output). Output low when synchronized with paging system. ADRDET 20 O Active high while the user IA detected in the address partition. (normally Low) MSGVAL 21 O MSGVAL will be active during MCLK, MDATA available period. Active high/low is dependent on MSGI option bit. MDATA 22 O Serial paging message output to µC. Rising/falling edge is dependent on MCKEG option bit. UDI1 −0 used to select interval per bytes MDATA. MCLK 23 O Serial clock output to µC for available paging message. MCKI used to select initial state, and MCK1, MCK0 used to select clock rate. ENLED 24 I Internal pull low, Active high to enable LEDO output. TEST1 25 I Test only. No connection for normal operation TEST2 26 O Test only. No connection for normal operation LEDO 27 O 10/4 kHz or 40/16 kHz CMOS clock output. VDD 28 I 3 volts power supply. |
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Similar Description - W93910 |
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