844101AGI-312

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 28, 2005

1

Integrated

Circuit

Systems, Inc.

ICS844101I-312

PRELIMINARY

The ICS844101I-312 is a low phase-noise

frequency margining synthesizer and is a mem-

ber of the HiPerClock S™ family of high perfor-

mance clock solutions from ICS. In the default

mode, the device nominally generates a

312.5MHz LVDS output clock signal from a 25MHz crystal

input. There is also a frequency margining mode available

where the device can be programmed, using the serial in-

terface, to vary the output frequency up or down from nomi-

nal in 2% steps. The ICS844101I-312 is provided in a 16-

pin TSSOP.

• One 312.5MHz nominal LVDS output

• Selectable crystal oscillator interface designed for 25MHz,

18pF parallel resonant crystal or LVCMOS single-ended

input

• Output frequency can be varied in 2% steps ± from nominal

• VCO range: 560MHz - 690MHz

• RMS phase jitter @ 312.5MHz, using a 25MHz crystal

(1.875MHz-20MHz): 0.52ps (typical)

• Output supply modes

Core/Output

3.3V/3.3V

3.3V/2.5V

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-complaint

packages

HiPerClockS™

ICS

GND

S_LOAD

S_DATA

S_CLOCK

SEL

OE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MODE

Q

nQ

GND

CLK

XTAL_OUT

XTAL_IN

ICS844101I-312

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm

package body

G Package

Top View

1

1

0

Phase

Detector

VCO

560 - 690MHz

÷ M

OSC

÷ N

÷ P

Serial Control

Q

nQ

Pullup

Pulldown

Pulldown

Pulldown

Pulldown

Pulldown

OE

CLK

SEL

S_CLOCK

S_DATA

S_LOAD

MODE

XTAL_IN

XTAL_OUT

Pulldown

25MHz

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on

initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications

without notice.