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ICS853001AGLFT Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS853001AGLFT Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 16 page 853001AG www.icst.com/products/hiperclocks.html REV. A JANUARY 29, 2005 1 Integrated Circuit Systems, Inc. ICS853001 1:1, DIFFERENTIAL LVPECL-TO- 2.5V, 3.3V, 5V LVPECL/ECL BUFFER GENERAL DESCRIPTION The ICS853001 is a 1:1 Differential LVPECL- to-LVPECL Buffer and a member of the HiPerClock S ™family of High Perfor mance Clock Solutions from ICS. The ICS853 001 may be used to regenerate LVPECL clocks which may have been attenuated, across a long trace, or may also be used as a differential-to-LVPECL translator. The differen- tial input can accept the following differential input types: LVPECL, LVDS and CML. The device also has an output en- able pin for debug/test purposes. When the output is disabled, it drives differential LOW (Q = LOW, nQ = HIGH). The ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on space-constrained boards. FEATURES • 1:1 Differential LVPECL-to-LVPECL / ECL buffer • 1 LVPECL clock output pair • 1 Differential LVPECL PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: >2.5GHz • Part-to-part skew: 100ps (maximum) • Propagation delay: 500ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • LVPECL mode operating voltage supply range: V CC = 2.375V to 5.25V, VEE = 0V • ECL mode operating voltage supply range: V CC = 0V, VEE = -5.25V to -2.375V • -40°C to 85°C ambient operating temperature • Lead-Free package RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT ICS853001 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View VCC Q nQ VEE 1 2 3 4 HiPerClockS™ ICS OE PCLK nPCLK VBB 8 7 6 5 Q nQ OE PCLK nPCLK V BB D Q LE ICS853001 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View |
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