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853054AL Datasheet(PDF) 9 Page - Integrated Circuit Systems

Part # 853054AL
Description  4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

853054AL Datasheet(HTML) 9 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
853054AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
9
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PRELIMINARY
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 3A and 3B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS


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