PE3291EK datasheet(7/15 Pages) PEREGRINE

Part #	PE3291EK

Description	1200 MHz / 550 MHz Dual Fractional-N FlexiPower??PLL for Frequency Synthesis

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

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Product Specification

PE3291

Page 7 of 15

Document No. 70-0009-04

│ www.psemi.com

Functional Description

The Functional Block Diagram in Figure 7 shows a

21-bit serial control register, a multiplexed output,

and PLL sections PLL1 and PLL2. Each PLL

contains a fractional-N main counter chain, a

reference counter, a phase detector, and an

internal charge pump with on-chip fractional spur

compensation. Each fractional-N main counter

chain includes an internal dual modulus prescaler,

supporting counters, and a fractional accumulator.

Serial input data is clocked on the rising edge of

Clock, MSB first. The last two bits are the address

bits that determine the register address. Data is

transferred into the counters as shown in Table 8,

PE3291 Register Set. If the foLD pin is configured

as data out, then the contents of shift register bit

S20 are clocked on the falling edge of Clock onto

the foLD pin. This feature allows the PE3291 and

compatible devices to be connected in a daisy-

chain configuration.

The PLL1 (RF) VCO frequency fin1 is related to

the reference frequency fr by the following

equation:

fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1)

(1) Note that A1 must be less than M1. Also, fin1

must be greater than or equal to 1024 x (fr/R1) to

obtain contiguous channels.

The PLL2 (IF) VCO frequency fin2 is related to the

reference frequency fr by the following equation:

fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2)

(2) Note that A2 must be less than M2. Also, fin2

must be greater than or equal to 256 x (fr/R2) to

obtain contiguous channels.

F1 sets PLL1 fractionality. If F1 is an even number,

the PE3291 automatically reduces the fraction.

For example, if F1 = 12, then the fraction 12/32 is

automatically reduced to 3/8. In this way,

fractional denominators of 2, 4, 8, 16 and 32 are

available. F2 sets the fractionality for PLL2 in the

same manner.

Figure 7. Functional Block Diagram

32/33

Prescaler

f

in1

Fractional Spur

Compensation

Fractional Spur

Compensation

9-bit Reference

Divider

9-bit Reference

Divider

21-bit Serial Control

Interface

Ref.

Amp.

f

r

Clock

Data

LE

f

in2

16/17

Prescaler

f

oLD

CP1

CP2

Phase

Detector

Phase

Detector

Charge

Pump

Charge

Pump

Multiplexer

A

1 Counter

0<A

1<31

A

2 Counter

0<A

2<15

Prescaler

Control Logic

Prescaler

Control Logic

M

1 Counter

3<M

1<511

M

2 Counter

3<M

2<511

F

2 Counter

0<F

2<31

F

1 Counter

0<F

1<31

R

2

9

R

1

9

M

2

9

F

2

5

A

2

4

A

1

5

M

1

9

F

1

5

C

22

C

21

C

11

C

12

P

1

P

2

P

1

P

2

C

22

C

22

C

22

C

22

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