PE3340

Advance Information

Copyright

Page 9 of 12

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Reserved**

Bit 1

Reserved**

Bit 2

Drives the M counter output onto the Dout output.

Bit 3

Power down

Power down of all functions except programming interface.

Bit 4

Counter load

Immediate and continuous load of counter programming.

Bit 5

MSEL output

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Bit 6

Drives the reference counter output onto the Dout output

Bit 7

Reserved**

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

PD_D. If the divided VCO leads the divided

pulses “low”. If the divided reference leads the

PD_U pulses “low”. The width of either pulse is

directly proportional to phase offset between the

The phase detector gain is equal to 2.70 V / 2

π,

which numerically yields 0.43 V / Radian.

PD_U and PD_D drive an active loop filter which

controls the VCO tune voltage. PD_U pulses result

in an increase in VCO frequency and PD_D results

in a decrease in VCO frequency, for a positive Kv

VCO.

A lock detect output, LD is also provided, via the pin

Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2 kohm resistor. Connecting Cext to an external

shunt capacitor provides low pass filtering of this

signal. Cext also drives the input of an internal

inverting comparator with an open drain output.

Thus LD is an “AND” function of PD_U and PD_D.