27-Bit, 2.5MHz-to-42MHz

DC-Balanced LVDS Serializer

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3

AC ELECTRICAL CHARACTERISTICS

°C.) (Note 3)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PCLK_IN TIMING REQUIREMENTS

Clock Period

Figure 2

23.8

400.0

ns

Clock Frequency

2.5

42.0

MHz

Clock Frequency Difference from

Deserializer Reference Clock

-2

+2

%

Clock Duty Cycle

DC

35

50

65

%

Clock Transition Time

Figure 2

2.5

ns

SWITCHING CHARACTERISTICS

PRE = low

280

370

Output Rise Time

20% to 80%,

≥ 250mV, Figure 3

PRE = high

240

320

ps

PRE = low

280

370

Output Fall Time

80% to 20%,

≥ 250mV, Figure 3

PRE = high

240

320

ps

Input Setup Time

Figure 4

3

ns

Input Hold Time

Figure 4

3

ns

DC ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Differential Output Resistance

78

110

147

Ω

PRE = 0

15

25

2.5MHz

PRE = 1

27

PRE = 0

18

25

5MHz

PRE = 1

27

PRE = 0

23

28

10MHz

PRE = 1

30

PRE = 0

33

39

20MHz

PRE = 1

42

PRE = 0

50

65

35MHz

PRE = 1

69

PRE = 0

60

70

Worst-Case Supply Current

Ω ±1%,

continuous 10

transition words

42MHz

PRE = 1

75

mA

Power-Down Supply Current

(Note 4)

50

µA